1. Field of the Invention
The present invention relates to a testing circuit for a semiconductor device, and more specifically to a testing circuit, a testing method, and a semiconductor chip that make it hard to decrypt or falsify the data in a chip.
2. Description of the Related Art
A semiconductor device is used in various industrial fields and functions as the base of industries. It is very important to secure the reliability of the semiconductor device. Therefore, when conducting a test of a semiconductor device, it should include not only the operation test of a logic circuit, but also tests of the rewritable non-volatile memory, such as built-in EEPROM, flash memory, FeRAM (Ferroelectric Random Access memory), etc. In this case, a dedicated memory test mode is more appropriate than using a BIST (built-in self-test) circuit to test the memory requiring a special sequence for rewriting data.
Accordingly, so far a testing pad is formed in a chip, ROM with an application for setting a test mode is formed in a chip, and the ROM is accessed from the testing pad, thereby testing the memory and logic circuit in the chip.
The invention of Japanese Published Patent Application No. 2001-135597 (Japanese Patent Application Publication) discloses the technology for preparing a pad in a scribe area (cutting area) in which a semiconductor wafer is cut and then cutting the wafer after writing data on the storage area of the chip. This thereby separates the pad from the chip and prevents the decryption of data.
However, in the conventional testing method of storing a testing pad and ROM with an application for setting a test mode in a chip, it is possible for a third party to decrypt the memory and logic in the chip by accessing the ROM from the testing pad, thereby possibly causing what is called a security hole.
In the semiconductor device described in the Japanese Published Patent Application No. 2001-135597, the scribe pad is cut, but ROM remains in the chip, thereby failing to solve the above-mentioned problem.